This invention relates in general to semiconductor devices and, more particularly, to a means and method for providing an insulating isolation wall for electrically isolating one portion of an integrated semiconductor device structure or circuit from another. The isolation wall is formed in a trench provided in the semiconductor substrate.
The copending application by Robert Mattox et al., Ser. No. 07/122,086, entitled "Trench Isolation Process and Structure", and the copending application of Andrew G. Nagy et al.,, Ser. No. 07/122,094, now U.S. Pat. No. 4,791,073 entitled "Trench Isolation Method for Semiconductor Devices", are related and are incorporated herein by reference.
It is common place to provide isolation walls between adjacent devices or device regions in integrated circuits, particularly bipolar integrated circuits. In the prior art these isolation walls have been formed of a dielectric such as silicon dioxide or a combination of silicon dioxide and polycrystalline silicon. A disadvantage of using thermally grown silicon dioxide for the isolation walls is that oxide growth progresses laterally as well as vertically making achievement of small lateral dimensions and precise dimensional control more difficult. In addition, trapped voids are frequently formed when oxide is used, particularly in trenches whose depth is equal to or larger than their width.
Further, silicon dioxide, which is the most commonly used trench refill material, whether grown or deposited, has a different coefficient of thermal expansion than most semiconductor substrates. As a consequence, when the semiconductor wafer is heated and cooled during processing, the differential thermal expansion can induce great stress in the semiconductor substrate. This leads to defect formation in the substrate adjacent to the isolation wall, which is undesirable.
It is known in the prior art to replace part of the dielectric of the isolation wall with a polycrystalline semiconductor of the same material as the substrate. The poly region is isolated from the substrate by a thin oxide region on the sides of the trench or is doped so as to form a PN junction with the single crystal semiconductor substrate or both. While the use of such a poly plug in the isolation wall trench can reduce the differential thermal expansion mismatch, it creates other problems well known in the art.
As described in the copending applications by Mattox et al., and Nagy et al., noted above, the thermal mismatch and other problems can be overcome by use of an oxynitride trench filling material. However, some problems still remain, particularly where trenches of different widths must be consistently filled on the same substrate in a manner which avoides cracks, crevices, voids and lack of planarity, independent of trench width.
Accordingly, it is an object of the present invention to provide an improved means and method for isolation walls for semiconductor devices and integrated circuits.
It is an additional object of the present invention to provide an improved means and method for isolation walls for semiconductor devices and integrated circuits having isolation walls of different widths in the same wafer.
It is a further object of the present invention to provide an improved means and method for isolation walls for semiconductor devices and integrated circuits having isolation walls of different widths in the same wafer, wherein the dielectric filling in the isolation trenches is formed in a single reactor.
It is an additional object of the present invention to provide an improved means and method for isolation walls for semiconductor devices and integrated circuits having isolation walls of different widths in the same wafer, wherein mid-trench crevices or gaps are avoided.
It is a further object of the present invention to provide an improved means and method for isolation walls for semiconductor devices and integrated circuits having isolation walls of different widths in the same wafer, wherein the dielectric filling the isolation trenchs has a controlled and minimal differential thermal expansion relative to the substrate, independent of trench width.
It is an additional object of the present invention to provide an improved means and method for isolation walls for semiconductor devices and integrated circuits employing isolation walls of different widths in the same wafer, wherein the foregoing objectives are achieved simultaneously.